1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device which comprises a circuit for writing data to a memory cell.
2. Description of the Related Art
A writing operation of a conventional semiconductor memory device such as a dynamic random access memory (DRAM) will be described. FIG. 57 is a circuit diagram showing a part of a DRAM configuration. This DRAM comprises a memory cell array in which memory cells MC are arranged in a matrix form, a plurality of bit line pairs BL, /BL, a plurality of word lines, a precharge circuit 2, a sense amplifier circuit 4, a DQ gate 5, and data line pairs DQ, /DQ (only one memory cell is representatively shown).
The memory cell MC is configured by serially connecting a cell transistor CT and a capacitor CC. A reference voltage VPL is supplied to the memory cell MC. A precharge voltage VBL is supplied to the precharge circuit 2. The precharge circuit 2 supplies VBL to the bit line pair BL, /BL by activating a bit line precharge signal BLP. At this time, the VBL is equal to a high-level bit line voltage VBLH, (VBLH−VBLL)/2, a low-level bit line voltage VBLL, another other potential or the like.
The high-level bit line voltage VBLH and the low-level bit line voltage VBLL are supplied to the sense amplifier circuit 4. The sense amplifier circuit 4 amplifies data of the bit line pair BL, /BL by activating sense amplifier activation signals SEN and SEP. The DQ gate 5 transfers data between the data line pair DQ, /DQ and the bit line pair BL, /BL by activating a column selection signal CSL.
FIG. 58 is a timing chart of the DRAM shown in FIG. 57. It is to be noted that VDD represents a power supply voltage of a peripheral logic portion, VPP represents a word line driving voltage boosting the VDD, and VSS represents a ground voltage.
The bit line precharge signal BLP changes from a “H” level (e.g., VPP, VBLH, VDD) to a “L” level (VSS) to release the precharging of the bit line pair BL, /BL. When a word line WL changes from a “L” level (VSS) to a “H” level (VPP), data stored in the memory cell MC appear in the bit line pair BL, /BL.
After the passage of certain time, the signal SEN is changed from a “L” level (VSS) to a “H” level (e.g., VBLH, VDD), and the signal SEP is changed from a “H” level (e.g., VBLH) to a “L” level (VSS), whereby the data appearing in the bit line pair BL, /BL are amplified.
Accordingly, the bit line of the high-level side becomes VBLH, while the bit line of the low-level side becomes VBLL (VSS normally). Then, by changing the column selection signal CSL from a “L” level (VSS) to a “H” level (e.g., VDD, VBLH), the data of the bit line pair BL, /BL are transferred to the data line pair DQ, /DQ in the case of reading. On the other hand, in the case of writing, the data of the data line pair DQ, /DQ are transferred to the bit line pair BL, /BL. Thus, a writing operation is performed.
Meanwhile, to meet a demand for high device performance (high-speed operation, suppression of power consumption), miniaturization based on a scaling rule has progressed, and a power supply voltage applied to the transistor in the chip has been lowered from generation to generation. With further miniaturization in the future, however, the fall of power supply voltage will probably become a large problem in designing of a semiconductor memory.
The fall of power supply voltage must be accompanied by a fall of threshold voltage of the transistor. However, for example, an increase of cell leakage caused by the fall of threshold voltage becomes a problem in a static random access memory (SRAM). In the DRAM, the progress in miniaturization has brought about a difficulty of securing a cell capacity or suppressing leakage current. Consequently, when the power supply voltage (high-level bit line voltage VBLH) is lowered, the amount of charges accumulated in the cell is reduced, deteriorating data saving performance.
To deal with the problem, the power supply voltage of the memory cell portion will have to be set higher than that of the peripheral logic portion in the future. In such a case, as shown in FIG. 59, external circuits (including DQ buffer) outside the data line pair DQ, /DQ operate by the same voltage VDD as that of the peripheral logic portion to suppress power consumption, while the sense amplifier circuit 4 operates by VBLH or the like, which is a voltage higher than the voltage VDD.
When a transistor of a type different from that of the peripheral logic portion is used in the memory cell portion of a high power supply voltage (e.g., transistor used at a low voltage has characteristics such as a short gate length, a thin gate oxide film and the like for the purpose of achieving a high speed), from the standpoint of reliability, the voltage VBLH used for the sense amplifier circuit 4 must not be applied to the circuits outside the data line pairs DQ, /DQ.
A simplest method as countermeasures is to drive the signal CSL by VDD. Then, when data reverse to that held in the sense amplifier circuit 4 is written to the memory cell MC at the time of writing, i.e., when the data of the bit line pair BL, /BL must be reversed, the data held in the sense amplifier circuit 4 by a voltage VBLH must be reversed by the DQ gate 5 driven by VDD lower than the VBLH. Thus, the data cannot be reversed unless a size of the transistor constituting the DQ gate 5 is set very large.
As other countermeasures, a method of making sizes of transistors (sense amplifier pair transistor, sense amplifier driver) constituting the sense amplifier circuit 4 small may be employed. In this case, however, a transition speed of the bit line pair BL, /BL becomes slow. Thus, unless deactivation timing of the word line WL is delayed, a voltage level of data stored in the memory cell MC during restoring (rewriting of data read to the bit line) and writing to the memory cell MC is lowered.
Conventional configurations of an sense amplifier driver (SA driver) and a common source line (NCS, PCS) are as follows.
To begin with, when only one SA driver (NSA driver, PSA driver) is arranged in a sense amplifier control circuit or the like for a sense amplifier bank (SA bank) constituted of a plurality of sense amplifiers, as shown in FIG. 60, sense amplifier circuits of all columns in the SA bank must be connected to one common source line connected to the SA driver. As shown in FIG. 61, for example, the sense amplifier control circuits are arranged in areas adjacent to the SA bank and a row decoder.
Next, when a plurality of SA drivers are arranged in the SA bank, the plurality are arranged corresponding to WL stitch areas (in the case of a layered WL configuration, area in which the SA bank and a sub WL driver area intersect each other) present in a plurality of places in the SA bank. In this case, at least the sense amplifiers of all the columns in the SA bank must be classified for each WL stitch area, and each classified sense amplifier group must be connected to the common source line connected to the SA driver arranged in each WL stitch area. Further, for a reason below, the sense amplifier circuits of all the columns in the SA bank are connected to one common source line.
When a plurality of SA drivers are arranged in the SA bank, in a period until potentials (high-level/low-level) of the bit line pairs BL, /BL determine by activating the sense amplifier circuit, the sense amplifier circuits of all the columns simultaneously perform sense operations. Thus, during this period, driving efficiency of all the plurality of SA drivers is distributed and assigned to all the columns.
However, in the case of a writing operation, normally, data of only a column to which writing is carried out from a state in which potentials (high-level/low-level) of bit line pairs BL, /BL of all the columns in the SA bank determined by activating the sense amplifier circuit is rewritten. At this time, if the plurality of SA drivers are all connected to the common source line connected to the sense amplifier circuit of the column to which the writing is carried out, the driving efficiency of all the plurality of SA drivers can be concentrated on the column to which the writing is carried out, and a writing speed can be made fast (especially, in the PSA driver). Thus, to achieve the highest writing speed, the sense amplifier circuits of all the columns and all the SA drivers are connected to one common source line.
As the common source line is connected to the sense amplifier circuits of all the columns, the SA drivers may be arranged in any places on the common source line. Such high layout freedom of the SA drivers enables optimization of the layout of the entire SA bank as a result, making it possible to minimize an area of the entire SA bank.
For example, in Document 1 (Published Japanese Patent No. 3202580) and Document 2 (Jpn. Pat. Appln. KOKAI Publication No. 2002-208277), by setting an arranging pitch of a layout repeating unit in the SA bank smaller than a pitch of a bit line, a space is created in the SA bank, and the SA driver is arranged therein to make an area of the entire bank very compact. If the sense amplifier circuits of all the columns and all the SA drivers are connected to one common source line in the SA bank, such a layout can be easily realized.
Further reasons that the sense amplifier circuits of all the columns in the SA bank must be connected to one common source line are as follows.
If there is a leakage source (e.g., junction leakage due to a crystal defect) somewhere in the common source line, a potential of the common source line is somehow set equal to a well potential (e.g., P well potential (VSS or the like) in the case of NCS). This potential change of the common source line is similar to that of the common source line during the sense amplifier circuit operation. Thus, if the leakage causes a fall of the potential of the common source line to a certain level, before a sufficient signal is output from the cell to the bit line BL after the precharging of the BL is released, a sense operation is started (slowly), creating a possibility of an erroneous operation.
Thus, to prevent such an erroneous operation, the common source line must be precharged while the sense amplifier circuit is inactive. In other words, by precharging the common source line, even if leakage occurs in the commons source line, the potential of the common source line can be maintained at a level for preventing unintended operation start of the sense amplifier circuit. In reality, in the precharge period of a ½ VBLH precharge system, by short-circuiting the NCS of a VSS potential and the PCS of a VBLH potential, and connecting them to a VBL power source (bit line precharge power source, equal to ½ VBLH here), they are quickly precharged to VBL potentials. Accordingly, the precharge potential of the common source line is equal to the precharge potential VBL (not necessarily ½ VBLH) of the bit line.
Incidentally, the precharge transistor (FIG. 62) of the common source line is originally designed to compensate for a leakage current which is not large and to maintain the common source line at the VBL potential. Thus, its size does not need to be large. Arrangement of such a small precharge transistor for each column, or for some columns leads to low layout efficiency. That is, because of a design rule and to guarantee device characteristics, even if very small transistors are arranged for some columns, sizes thereof may be larger than necessary.
Even if transistors of necessary sizes can be arranged for some columns, a layout space in which nothing is arranged may be formed between the precharge transistors. Accordingly, by connecting the sense amplifier circuits of all the columns in the SA bank to the common source line, and arranging the precharge transistor in the sense amplifier circuit or the WL stitch area to be shared by many columns, an area increase caused by the arrangement of precharge transistors can be virtually eliminated.
As the common source line is connected to the sense amplifier circuits of all the columns, the precharge transistor may be arranged in any place on the common source line. For example, even in the case of arrangement in the WL stitch area, it is not necessary to arrange precharge transistors in all the WL stitch areas. In this case, other devices can be arranged in the WL stitch areas in which precharge transistors are not arranged.
As described above, as long as the common source line is connected to the sense amplifier circuits of all the columns, the layout freedom of the precharge transistors can be increased. As a result, the layout of the entire SA bank can be optimized, making it possible to minimize the layout area of the entire SA bank.
As described above, the power supply voltage of the memory cell portion will have to be set higher than that of the peripheral circuit portion (logic portion), making difficult the writing operation of the semiconductor memory in the future. Under such circumstances, connecting of the sense amplifier circuits of all the columns and all the SA drivers in the SA bank to the common source line to achieve a high writing speed makes the writing operation more difficult. Then, in reality, there will be no practical solutions.
Furthermore, when the miniaturization is accompanied by a fall of potential amplitude of the bit line connected to the memory cell, the threshold voltage of the NMOS sense amplifier transistor or the PMOS sense amplifier transistor must be lowered to realize a stable sense operation. When the threshold voltage falls to a certain level or lower, a reduction of a signal on the bit line BL during signal development due to an influence of a leakage current via the NMOS sense amplifier transistor or the PMOS sense amplifier transistor cannot be ignored any more, and this influence is larger as the number of columns connected to the common source line is larger.